Over the past 30 years, developments in silicon-based integrated circuit technology, such as metal-oxide-semiconductor (MOS) devices including field effect transistors (FETs and/or MOSFETs), have provided greater device speed, increased integration density, and improved device functionality with reduced cost. Referring to FIG. 1A, MOS devices are typically formed in a substrate 10 having heavily-doped source/drain (S/D) regions 12 separated by a more lightly-doped channel region 18. The channel region 18 may be controlled by a gate electrode 14 that is separated from the channel region by a gate dielectric 16.
However, with increasing requirements for higher integration as well as higher performance, lower power dissipation, and greater economic efficiency, a variety of problems associated with degradation of transistor characteristics may arise. For example, as the channel length of a transistor is reduced, short-channel effects such as punch-through, drain induced barrier lowering (DIBL), sub-threshold swing, increased parasitic capacitance between a junction region and the substrate (i.e. junction capacitance), and increased leakage current may occur.
A variety of transistor designs have been developed which may address some of the problems faced by conventional bulk-MOS semiconductor devices. For example, FIG. 1B illustrates a conventional ultra-thin body transistor. In an ultra-thin body transistor, the channel region 18 may be formed in a thin layer above an insulating region. Also, FIG. 1C illustrates a conventional double-gate transistor. In a double gate transistor, a single channel region 18 may be controlled by two gates 14a and 14b that are separated from the channel region by gate dielectrics 16a and 16b. As such, both sides of the channel region may be controlled.
However, the devices of FIGS. 1B and 1C may require more complex fabrication techniques, which may increase cost and decrease yield. Accordingly, such devices may be less practical in general semiconductor manufacturing.
For example, ultra-thin body transistors may be considerably more expensive to produce than conventional bulk-MOS devices. Although they may provide improved performance in some areas, ultra-thin body transistors may be susceptible to floating body and heat transfer effects, and may have current limitations imposed by the body thickness.
In addition, by controlling the channel from two sides, double-gate devices may exhibit improved leakage performance. However, double-gate devices may require a more complex fabrication processes, which may increase expense and lower yield. More particularly, it may be difficult to align upper gate 14a and lower gate 14b (as shown in FIG. 1C) in double-gate transistor fabrication.
FinFET transistors, in which the channel region is formed in a vertically protruding “fin” of semiconductor material, may provide leakage performance similar to or better than that of double-gate transistors, but may be less complicated and less expensive to produce. FinFET transistors (or simply FinFETs) may also support scaling to sub-50 nm channel lengths (and perhaps as low as 10 nm), which may provide additional improvements in integration density and operational speed.
In FinFETs, the channel region may be formed in a vertically oriented fin-shaped active region protruding from the semiconductor substrate, as discussed above. The gate dielectrics may be formed on the fin, and the gate electrode may be formed around the fin. The channel region may be formed first, followed by source and drain regions. The source/drain regions may be taller than the fin. Dielectric and conductive materials may then be used to form double- and/or triple-gate devices.
FIGS. 2A to 2D are cross-sectional views of a semiconductor substrate illustrating conventional methods for forming a FinFET.
Referring now to FIG. 2A, an etch mask pattern 13 is formed on a silicon substrate 10. A portion of the silicon substrate 10 exposed by the etch mask pattern 13 is anisotropically etched to form a silicon fin 15. An upper edge of the silicon fin 15 is formed at a sharp angle (i.e. at nearly a right angle) due to the anisotropic etching. The etch mask pattern 13 may be formed of nitride, and a thermal oxide layer may be formed between the nitride and substrate. In order to provide electrical insulation between neighboring silicon fins, a device isolation layer 17 is formed, as shown in FIG. 2B.
Referring now to FIG. 2C, a portion of the device isolation layer 17 is removed, exposing lateral surfaces, or sidewalls, of the silicon fin 15. The lateral surfaces of the silicon fin 15 may serve as a channel region for a transistor.
Referring to FIG. 2D, a gate insulating layer 19 is formed on the exposed sidewalls of the silicon fin 15, and a gate electrode 21 is formed to create a double-gate FinFET. Both sidewalls of the silicon fin 15 may be controlled by the gate electrode 21.
According to conventional methods for forming double-gate FinFETs, adhesion between the etch mask pattern 13 and the substrate 10 may be weakened when a portion of the device isolation layer 17 is removed. Since the device isolation layer 17 may also be formed of an oxide, a thermal oxide layer of the etch mask pattern 13 on a portion of silicon fin may be removed along with the portion of the device isolation layer 17. As the width of the silicon fin 15 may be decreased to allow for higher device integration, it may be increasingly possible for the etch mask pattern 13 to be separated from the upper surface of the silicon fin 15. If the etch mask pattern is removed, an upper surface of the silicon fin 15 may be controlled by the gate electrode 21, and a triple-gate FinFET may be formed. Accordingly, double-gate and triple-gate FinFETs may be formed on the same wafer.
Still referring to FIG. 2D, in order to form higher-performance devices, the width of the silicon fin 15 may be decreased by performing a thermal oxidation process before forming the gate insulating layer 19. In other words, the width of the silicon fin 15 may be reduced by forming a sacrificial oxide layer at sidewalls of the fin 15 using a thermal oxidation process, and then removing the sacrificial oxide layer. As such, the fin 15 may have a width narrower than that of the etch mask pattern 13. Accordingly, an under-cut region may be formed under the etch mask pattern 13, resulting in poor step coverage during subsequent processes, such as the deposition of gate electrode material. In addition, if the sacrificial oxide layer is removed, the thermal oxide layer of the etch mask pattern 13 may also be partially removed. As a result, the etch mask pattern 13 may be separated from the silicon fin 15, and the problems described above may occur.
Triple-gate FinFETs have been developed which may address some of these problems. In triple-gate FinFETs, an upper surface and both sidewalls of the silicon fin are controlled by a gate electrode, which may improve current driving capacity.
A conventional method for forming a triple-gate FinFET will be described with reference to FIGS. 3A to 3B. Triple-gate FinFETs can be formed by removing the etch mask pattern in the conventional methods for forming double-gate FinFETs described above with reference to FIGS. 2A to 2D.
As shown in FIG. 2B, a silicon fin 15 and a device isolation layer 17 are formed. Then, as shown in FIG. 3A, a portion of the device isolation layer 17 and an etch mask pattern 13 are removed. As a result, both sidewalls and an upper surface of the silicon fin 15 are exposed.
Referring to FIG. 3B, a gate insulating layer 19 is formed on the exposed surfaces (i.e. both sidewalls and the upper surface) of the silicon fin 15, and then a gate electrode 21 is formed.
However, a “hump” in subthreshold current may occur during operation of such a triple-gate FinFET. In other words, if an upper edge or corner of the silicon fin is sharp, and if a gate electrode controls both the sidewalls and the upper surface of the silicon fin, an electric field may be concentrated at the sharp edge portion (i.e., at the corner where both sidewalls and the upper surface of the silicon fin meet). As such, leakage current may be present at voltages below the transistor threshold voltage.